Analog Circuit Design Techniques at 0.5 V by Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis

By Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis Tsividis, Peter Kinget

Analog layout at ultra-low provide voltages is a vital problem for the semiconductor study neighborhood and industry.

Analog Circuit layout thoughts at 0.5V covers demanding situations for the layout of MOS analog and RF circuits at a 0.5V strength offer voltage. All layout concepts awarded are real low voltage strategies - all nodes within the circuits are in the strength provide rails. The circuit implementations of physique and gate enter absolutely differential amplifiers also are mentioned. those construction blocks let us to construct continuous-time filters, track-and-hold circuits, and continuous-time sigma delta modulators.

Current books on low voltage analog layout quite often hide innovations for provide voltages right down to nearly 1V. This publication provides novel rules and effects for operation from a lot reduce provide voltages and the strategies awarded are easy circuit strategies which are commonly acceptable past the scope of the offered examples.

Analog Circuit layout options at 0.5V is written for analog circuit designers and researchers in addition to graduate scholars learning semiconductors and built-in circuit design.

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52 3 Weak Inversion MOS Varactors for Tunable Integrators I = jωCgs V DUT G B S -VGS V G + − − + Ceff Reff − + V GB S Agilent 4284A LCR meter Fig. 2: Cgs measurement setup using Agilent 4284A LCR meter. which reduces the quality factor of the capacitor. The resistance measured in series with the capacitance at 1 MHz is shown in Fig. 3(c). The significant series resistance can be attributed to distributed effects – the source and the drain are connected outside the device, but internally there is a large channel resistance between them.

The bias voltages at all the nodes in the circuit are indicated. 7 Summary 45 common-mode feed-forward circuitry in Fig. 8(b) can be included to improve the common-mode rejection of this OTA input stage. 2 Bias circuits The switching threshold voltage of the error amplifiers discussed in Fig. 12 are controlled by the voltage Vamp . This voltage, applied to the body of the nMOS device in the error amplifier, controls the threshold voltage of the nMOS devices in each error amplifier. Through an active feedback loop, Vamp is controlled to set the switching threshold voltage of the error amplifier to VDD /2, as shown in Fig.

4 V ) VDD (b) Fig. 7 shows amplifier configurations using resistive feedback around an OTA. For this discussion let us assume that the input of the OTA consists of nMOS devices. A similar argument can be made for input pMOS devices. For a maximal output signal swing, the output common-mode level, Vcm,o , is typically set to VDD /2. Since the input of each stage is driven from a similar stage, the input common-mode level, Vcm,i , is also VDD /2. In order to turn the input devices of the OTA on, the virtual ground common level, Vcm,vg , needs to be set as high as possible.

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