Analog Circuit Design Techniques at 0.5V (Analog Circuits by Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis

By Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis Tsividis, Peter Kinget

This publication tackles demanding situations for the layout of analog built-in circuits that function from ultra-low strength offer voltages (down to 0.5V). assurance demonstrates the sign processing circuit and circuit biasing methods during the layout of operational transconductance amplifiers (OTAs). those amplifiers are then used to construct analog approach features together with non-stop time clear out and a pattern and carry amplifier.

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Extra info for Analog Circuit Design Techniques at 0.5V (Analog Circuits and Signal Processing)

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27. The output amplitude for a 1% total harmonic distortion is differential 712 mV peak-peak. 5 V R/2 R/2 PSRR Test Setup R/3 Vdd Fig. 18: Setup for measuring CMRR and PSRR of the OTAs. The dashed resistor is required for testing the gate-input OTA only. Open Loop Response 50 Measurement Gain (dB) Gain [dB], Phase [degrees] 0 dB Gain 0 Phase (degrees) Simulation −50 25 dB Gain Margin −100 −150 45o Phase Margin o −180 −200 2 10 4 10 Frequency [Hz] 6 10 Fig. 19: Simulation and measurements of the body-input OTA in open loop.

1. 1 Body-input OTA RC 21 CC Vin+ Vout+ Vout- Vin- RC CC Fig. 4: Two-stage OTA compensated with Miller capacitors and series resistors. 1: Transistor sizes and element values for the body-input OTA (Fig. 5 kΩ 6 pF devices, as shown in Fig. 1(b). Larger channel lengths will require, for the same performance, larger widths. This in turn will result in larger capacitances that the circuit will need to drive. 5 µm was chosen for all devices in this circuit as a compromise in the trade-off between lower VT , larger area requirements, and larger parasitic capacitance.

7 V [14,16,22–24]. In order to operate a MOS transistor at or near moderate inversion, a large voltage can be applied as a gate bias, and the signal can be applied to the body of the device. A very low voltage basic gain stage is shown in Fig. 2. The two inputs are at the bodies of pMOS transistors M1A and M1B , and their gmb provides the input transconductance. 25 V), the resulting small body-source forward bias lowers the VT and further increases the inversion level. Operation near the weakmoderate inversion boundary is preferred, in order to attain a relatively large body transconductance, gmb .

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