CMOS Integrated Switching Power Converters: A Structured by Gerard Villar Piqué

By Gerard Villar Piqué

This booklet describes the based layout and optimization of effective, strength processing built-in circuits. The procedure is multidisciplinary, overlaying the monolithic integration of IC layout concepts, strength electronics and keep watch over idea. specifically, this booklet allows readers to conceive, synthesize, layout and enforce built-in circuits with high-density high-efficiency on-chip switching strength regulators. themes lined surround the based layout of the on-chip energy provide, potency optimization, IC-compatible energy inductors and capacitors, strength MOSFET switches and effective change drivers in general CMOS applied sciences.

  • Provides a finished reference on established layout and optimization of absolutely monolithic strength offers for on-chip strength administration;
  • Describes a multidisciplinary strategy, encompassing more desirable built-in energy units, either energetic and reactive, in addition to complex circuit topologies and switching regulate equipment, including their implementation;
  • Enables concurrent layout of compact adaptive strength provides, including system-level and circuit-level techniques.


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Additional info for CMOS Integrated Switching Power Converters: A Structured Design Approach

Sample text

In order to obtain the total energy spent in each commutation, instantaneous power has to be integrated along the commutation interval (shaded area in Fig. 6).

3-level converter selected design main characteristics, referred to Io = 100 mA . . . . . . . . . . . . . . . . . . . . . . . . . Inductor optimized design characteristics . . . . . . . . . . . . . Co and C x capacitors optimized design characteristics . . . . . . . 3-level converter P1 and N1 power switches (and drivers) optimized design characteristics . . . . . . . . . . . . . . . . . . . . .

Transistor switching conditions for DCM and CCM operation . . . . Power loss expressions and trends for the MOSFET and driver designs Technological parameters information required to develope the design space exploration . . . . . . . . . . . . . . . . . . . . . . . Main characteristics of the optimized design before the application of the output ripple constraint . . . . . . . . . . . . . . . . . . . Complete set of characteristics of the optimized design after the application of the output ripple constraint .

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