CMOS Time-Mode Circuits and Systems: Fundamentals and by Fei Yuan

By Fei Yuan

Time-mode circuits, the place info is represented by means of time distinction among electronic occasions, supply a potential and technology-friendly capability to achieve mixed-mode circuits and platforms in nanometer complementary metal-oxide semiconductor (CMOS) applied sciences. a variety of architectures of time-based sign processing and layout recommendations of CMOS time-mode circuits have emerged; even if, an in-depth exam of the rules of time-based sign processing and layout options of time-mode circuits has no longer been available―until now.

CMOS Time-Mode Circuits and platforms: basics and Applications is the 1st e-book to convey a accomplished therapy of CMOS time-mode circuits and platforms. that includes contributions from major specialists, this authoritative textual content includes a wealthy choice of literature on time-mode circuits and systems.

The ebook starts off via featuring a severe comparability of voltage-mode, current-mode, and time-mode signaling for mixed-mode sign processing and then:

  • Covers the basics of time-mode sign processing, equivalent to voltage-to-time converters, all-digital phase-locked loops, and frequency synthesizers
  • Investigates the functionality features, structure, layout recommendations, and implementation of time-to-digital converters
  • Discusses time-mode delta-sigma-based analog-to-digital converters, putting an excellent emphasis on time-mode quantizers
  • Includes an in depth learn of ultra-low-power built-in time-mode temperature size systems

CMOS Time-Mode Circuits and platforms: basics and Applications presents a important reference for circuit layout engineers, method engineers, graduate scholars, and others looking to grasp this fast-evolving field.

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CMOS Time-Mode Circuits and Systems: Fundamentals and Applications

Time-mode circuits, the place details is represented by way of time distinction among electronic occasions, supply a conceivable and technology-friendly ability to achieve mixed-mode circuits and platforms in nanometer complementary metal-oxide semiconductor (CMOS) applied sciences. a variety of architectures of time-based sign processing and layout ideas of CMOS time-mode circuits have emerged; in spite of the fact that, an in-depth exam of the foundations of time-based sign processing and layout suggestions of time-mode circuits has now not been available―until now.

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Additional info for CMOS Time-Mode Circuits and Systems: Fundamentals and Applications

Example text

A time-mode integrated temperature sensor can also be realized using a temperature-dependent delay line whose delay is a linear function of temperature, a temperature reference line whose delay is independent of temperature and can be adjusted by changing its temperature setpoint, and a time comparator that discriminates the delay of the two delay lines. For a given temperature, the delay of the temperature reference can be made identical to that of the temperature-dependent delay line by digitally adjusting the delay of the temperature reference, that is, the temperature set point of the temperature reference line.

30) )>> It becomes evident that the arrangement of the polarity of the inputs of the two VCDLs maps a differential voltage to a differential time variable. Also, cascading 10 voltage-controlled delay stages provides a time amplification of 10, allowing a better detection of whether ΔτVCDL > 0 or not or equivalently vin > 0 or vin < 0. The price paid for the improvement of time accuracy through time amplification is the loss of speed. It should also be emphasized that since vin+ and vin- are applied to both VCDLs, the effect of mismatches between the two VCDLs is minimized.

Elsayed, M. Abdul-Latif, and E. Sanchez-Sinencio. A spur-frequency-boosting PLL with a −74 dBc reference-spur suppression in 90 nm digital CMOS. IEEE Journal of Solid-State Circuits, 48(9):2104–2117, September 2013. )>> C. Ljuslin, J. Christiansen, A. Marchioro, and O. Klingsheim. An integrated 16-channel CMOS time to digital converter. IEEE Transactions on Nuclear Science, 41(4):1104– 1108, August 1994. )>> P. Dudek, S. Szczepanski, and J. Hatfield. A high-resolution CMOS time-to-digital converter utilizing a vernier delay line.

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