Current Sense Amplifiers: for Embedded SRAM in by Bernhard Wicht

By Bernhard Wicht

This publication presents a scientific and complete perception into present sensing thoughts. as well as describing theoretical and useful points of present sensing, the writer derives sensible layout instructions for attaining an optimum functionality via a scientific research of other circuit rules. Voltage experience amplifiers also are thought of, for the reason that they're used as a last comparator in a present experience amplifier. leading edge thoughts, akin to reimbursement of the bitline multiplexer and auto-power-down, are elucidated. even though the focal point is on embedded static random entry reminiscence (SRAM), the cloth offered applies to any current-providing reminiscence variety, e.g. additionally to rising reminiscence applied sciences reminiscent of MRAM. The publication will attract layout engineers in and likewise to researchers wishing to profit approximately, and practice, present sensing techniques.

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Extra info for Current Sense Amplifiers: for Embedded SRAM in High-Performance System-on-a-Chip Designs

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The center and right-hand plots represent an enlarged section as marked by the gray box. , VSG = 400mV ~ vthp ' Larger VIND C results in smaller initial output voltage difference Vo (right) 30 3. Voltage Sense Amplifiers 95 90 #- 80 . 0V 80 75 .. V1NlmV 80 70 100 0. B 2 Fig. 12. Influence of VDD on the functional yield Y in relation to VIND C . left: yield vs. input voltage difference d VI N for different supply voltages; right: yield vs. 6VDD. This explains how the yield can be improved without decreasing the speed just by reducing the input dc level VI N DC.

9 Voo Fig. 14. Figure of merit for optimum VINDC . VINDC has been normalized by VDD to include different supply voltage values . Optimum VI N DC regarding yield (top) and speed (center) is det ermined by the maximum figure of merit FOM (bottom). FOM is defined as the ratio between yield and normalized delay. 2 A Latch-Type Sense Amplifier for Current Sensed SRAM 33 C, :4fF, o(ECL) = 10% 55 C/) --..... 0. 9 V1NOC I Voo Fig. 15. Standard deviation of sense amplifier delay ~tVSA = O"(tvSA) causes increased delay since it requires less VI N DC.

E. a voltage sense amplifier, will require a voltage signal the sensing delay has to be referred to the output voltage Vout rather than i out . As shown in Fig. 6, the parasitic capacitance C L at the output node causes an additional delay. 3) and Vout iin = G(s) rL 1 + srLCL the sensing delay can be calculated as the sum of both time constants Fig. 4. Small-signal equivalent circuit of Fig. 4 i!? v 0"' Fig. 5. Block diagram of Type A Fig. 6. 6) t= This confirms that high speed can be achieved by large transconductance gm' If the load capacitance G L is small and Tin large, the delay can be approximated by t ~ ~.

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